1. Field of the Invention
The present invention relates to a display device, and more particularly, relates to an array substrate for a liquid crystal display (LCD) device and a manufacturing method of the same.
2. Discussion of the Related Art
Our information-based society has an increasing demand for flat panel display (FPD) devices. FPD devices include plasma display panel (PDP) devices, field emission display (FED) devices, electroluminescent display (ELD) devices, liquid crystal display (LCD) devices, and so on. Since they are small and lightweight and have low power consumption, FPD devices are taking the place of cathode ray tube (CRT) display devices.
Among the various FPD devices, LCD devices are particularly useful in notebook computers and desktop monitors, because they provide excellent resolution, color display and image quality. An LCD device relies on optical anisotropy and polarizability of liquid crystal molecules to produce an image. Liquid crystal molecules are aligned with directional characteristics resulting from their long, thin shapes and are arranged at specified pre-tilt angles. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal molecules. Varying an applied electric field influences alignment of the liquid crystal molecules. Because of the optical anisotropy of liquid crystal molecules, refraction of incident light depends on the alignment direction of the liquid crystal molecules. Thus, by properly controlling the applied electric field, a desired image can be produced.
A typical LCD panel includes an upper substrate, a lower substrate facing the upper substrate, and a liquid crystal material layer interposed therebetween. An electric field is generated in the LCD panel by applying voltages to electrodes formed on the upper and lower substrates and changes alignment of the liquid crystal molecules, to thereby change light transmission and to display images.
In general, the LCD panel is fabricated by forming an array substrate that includes a thin film transistor as a switching element and a pixel electrode connected to the thin film transistor in a pixel region, forming a color filter substrate that includes at least red, green and blue color filters corresponding to the pixel region and a common electrode, attaching the array substrate and the color filter substrate by a seal pattern, and then injecting a liquid crystal material between the attached array substrate and color filter substrate.
A seal pattern generally contacts a passivation layer of the array substrate. In particular, because a passivation layer typically is formed of an organic insulating material, which has poor adhesion to a seal material, there exists a need to improve seal adhesion between the array substrate and the color filter substrate.
FIG. 1 is a plan view illustrating an array substrate for an LCD device according to the related art, and FIG. 2 is a cross-sectional view along II-II of FIG. 1. In FIG. 1, a substrate 10 includes a display area AA and a non-display area NA. The non-display area NA includes a gate link region GLA, a gate pad region GPA, a data link region (not shown), and a data pad region (not shown). In the display area AA, gate lines 12 are formed in a horizontal direction, and data lines 22 are formed in a vertical direction. The gate lines 12 and the data lines 22 cross each other to define pixel regions P, and a thin film transistor Tr is formed at each crossing of the gate lines 12 and the data lines 22.
In the gate pad region GPA, gate pads 42 are formed and are connected to outer driving circuits (not shown), and in the gate link region GLA, gate link lines 14 are formed and are connected to the gate pads 42 and the gate lines 12. Although not shown, in the data pad region, data pads are formed and are connected to the outer driving circuits, and the data link region, data link lines are formed and are connected to the data pads and the data lines 22. In addition, a passivation layer 38 is formed on the array substrate over the thin film transistor Tr, the gate lines 12, the gate link lines 14, and the data lines 22.
To attach the array substrate to a color filter substrate, a seal pattern 70 is formed on the passivation layer 38. In particular, the seal pattern 70 is disposed around the display area AA in the gate link region GLA and the data link region (not shown).
However, because the passivation layer 38 is formed of an organic insulating material, which has poor adhesion to the seal pattern 70, there exists a need to improve seal adhesion between the array substrate and the color filter substrate. Thus, through holes are made in the passivation layer 38, such that the seal pattern 70 contacts a layer other than the passivation layer.
Still, when the passivation layer 38 is etched for forming the through-holes, a gate insulating layer under the passivation layer is frequently etched due to thickness differences of the passivation layer or due to over-etching of the passivation layer to expose the gate link line 14. As a result, corrosion along the gate link line 14 is likely to occur. To address this problem, the dummy patterns 21 are formed under the passivation layer as an etch stopper.
In particular, a plurality of dummy patterns 21 are formed under the passivation layer 38 in the gate link region GLA, are in the same layer as the data lines 22, and has the same material as the data lines 22. Thus, the dummy pattern 21 has a multi-layered structure including an amorphous silicon layer 21a, a doped amorphous silicon layer 21b, and a metal layer 21c. 
In addition, the passivation layer 38 is etched to form a plurality of through-holes to expose the doped amorphous silicon layer 21b and the metal layer 21c of the dummy pattern 21. As a result, in addition to contacting the passivation layer 38, the seal pattern 70 also contacts the doped amorphous silicon layer 21b and the metal layer 21c, to thereby provide additional adhesion between the array substrate and the color filter substrate.
To effectively prevent the gate insulating layer 17 from being etched when the passivation layer 38 is patterned, the dummy pattern 21 has a larger size than the through hole 40. Thus, the metal pattern 21c remains at the edge portion of the dummy pattern 21. That is, a portion of the dummy pattern 21 has a three-layer structure and another portion has a two-layer structure.
Nonetheless, there may be electrical short between the metal pattern of the dummy pattern and the gate link lines. For example, when the array substrate and the color filter substrate are attached, the array substrate and the color filter substrate are under high voltage and high temperature for several hours and are pressured. The pressure can create cracks in the gate insulating layer and result hillock or migration of a metallic material for the gate link lines being in the cracks. Such metallic materials can contact the metal pattern of the dummy pattern causing an electric short and creating a defect.